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Your search returned 16 records. Click on the hyperlinks to view further details of Titles.. |
Magazine Name : Ieee Transactions On Very Large Scale Intergration (Vlsi) Systems
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Year : 2001 Volume number : 09 Issue: 05 |
A Nonseparable Vlsi Architecture For Two-Dimensional Discrete Periodized Transform
(Article)
Subject:
Computing
,
Design
,
Digital Filter
,
High Performance
Author:
K. C
Hung
Y. P
Hung
Y. J
Huang
page:
565
-
576
Technology Mapping For High-Performance Static Cmos And Pass Transistor Logic Designs
(Article)
Subject:
Physical Design
,
Technology Mapping
Author:
Y
Jiang
S. S
Sapatnekar
C.
Bamji
page:
577
-
589
A Low-Power High-Power High-Performance Current-Mode Multiport Sram
(Article)
Subject:
Current Mode Control
,
Low Power
,
Multiport Memory
Author:
Muhammad
Khellah
M. I
Elmasry
page:
590
-
598
Multilock Selection And Synthesis For Cdfgs Using Optimal Clock Sets And Genetic Algorithms
(Article)
Subject:
Clocks
,
Design Automation
,
Genetic Algorithm
,
High Level Synthesis
Author:
E.
Torbey
John P
Knight
page:
599
-
607
Power Estimation In Adiatic Circuits A Simple And Accurate Model
(Article)
Subject:
Cmos
,
Low Power Dissipation
,
Digital Cmos
Author:
M
Alioto
G
Palumbo
page:
608
-
615
On Gate Level Power Optimization Using Dual Supply Voltages
(Article)
Subject:
Dual Voltage
,
Gate-Level Simulation
Author:
C
Chen
A
Srivastava
M.
Sarrafzadeh
page:
616
-
629
Discrete Time Battery Model For System-Level Low Power Design
(Article)
Subject:
Batteries
,
Digital Systems
,
Energy Management
,
Power Demand
Author:
L
Benini
Giuliano
Castelli
A
Macii
page:
630
-
640
Narrow Bus Encoding For Low-Power Dsp Systems
(Article)
Subject:
Cmos
,
Low-Power
,
Switching Activity
,
System Level
Author:
Y
Shin
K
Choi
Y. H
Chang
page:
656
-
660
Delay Fault Testing Of Ip-Based Designs Via Symbolic Path Modeling
(Article)
Subject:
Automatic Test-Pettern Generation (Atpg)
,
Binary Decision Diagram(Bdd) Decomposition
,
Delay Fault Testing
Author:
H.
Kim
J. P
Hayes
page:
661
-
678
Resynthesis Of Combinational Logic Circuits For Improved Path Delay Fault Testability Using Comparison Units
(Article)
Subject:
Combinational Circuits
,
Design-For-Testability
,
Path Delay Default
Author:
I
Pomeranz
S. M.
Reddy
page:
679
-
689
Modelling Of Mixed Control And Dataflow Systems In Mascot
(Article)
Subject:
Codesign
,
Cosimulation
,
Embedded Systems
,
Matlab
Author:
P.
Bjureus
A.
Jantsch
page:
690
-
703
Statistical Skew Modeling For General Clock Distribution Networks In Presence Of Process Variations
(Article)
Subject:
Clock Distribution
,
Clock Skew
,
Maximal Clock Delay
,
Process Variations
Author:
Xiaohua
Jiang
Hironori
Horguchi
page:
704
-
717
On Effective Iddq Testing Of Low-Voltage Cmos Circuits Using Leakage Control Techniques
(Article)
Subject:
Low-Voltage
,
Reliability
Author:
Z
Chen
L
Wei
K
Roy
page:
718
-
725
Highly Parrallel And Energy-Efficient Exhaustive Minimum Distance Search Seacrh Engine Using Hybrid Digital/Analog Circuit Techniques
(Article)
Subject:
Digital/Analog- Mixed Circuits
,
Low-Power Design
,
Memory
Author:
C. H
Kwon
K
Lee
page:
726
-
729
An On-Chip March Pattern Generator For Testing Embedded Memory Cores
(Article)
Subject:
March Algorithm
,
Memory Testing
,
System-On-A-Chip (Soc)
Author:
Li
W.
K. J
Lee
page:
730
-
735
High-Speed Architectures For Reed-Solomon Decoders
(Article)
Subject:
Interleaved
,
Berlekamp--Massey Algorithm
Author:
M.A
Mansur
page:
]641
-
655
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